module systol_F (EXP) is ------------------------------------------------------------------------------- process MAIN [Y: WIRE] is hide X: WIRE in par X in GENERATOR [X] || ARRAY [X, Y] (W1, W2, W3, W4, W5, W6, W7) end par end hide end process ------------------------------------------------------------------------------- process GENERATOR [X: WIRE] is X (X1); X (X2); X (X3); X (X4); X (X5); X (X6); X (X7); X (X8); X (X9); X (X10); X (X11); X (X12); X (X13); X (X14); X (X15); X (X16); X (X17); X (X18); X (X19); stop end process ------------------------------------------------------------------------------- process ARRAY [X0: WIRE, Y: WIRE] (W1, W2, W3, W4, W5, W6, W7:EXP) is hide Y1, Y2, Y3, Y4, Y5, Y6, Y7: WIRE in par Y1, Y2, Y3, Y4, Y5, Y6, Y7 in hide X1, X2, X3, X4, X5, X6, X7: WIRE in par X1 -> CELL [X0, Y1, X1] (W7, 7) || X1, X2 -> CELL [X1, Y2, X2] (W6, 6) || X2, X3 -> CELL [X2, Y3, X3] (W5, 5) || X3, X4 -> CELL [X3, Y4, X4] (W4, 4) || X4, X5 -> CELL [X4, Y5, X5] (W3, 3) || X5, X6 -> CELL [X5, Y6, X6] (W2, 2) || X6 -> CELL [X6, Y7, X7] (W1, 1) end par end hide || ADDER [Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y] end par end hide end process ------------------------------------------------------------------------------- process CELL [X_IN, Y_OUT, X_OUT:WIRE] (W: EXP, in var K: NAT) is var X: EXP in loop X_IN (?X); if K > 1 then K := K - 1 else Y_OUT (W * X) end if; X_OUT (X) end loop end var end process ------------------------------------------------------------------------------- process ADDER [IN1, IN2, IN3, IN4, IN5, IN6, IN7, OUT: WIRE] is var Y1, Y2, Y3, Y4, Y5, Y6, Y7: EXP in IN1 (?Y1); IN2 (?Y2); IN3 (?Y3); IN4 (?Y4); IN5 (?Y5); IN6 (?Y6); IN7 (?Y7); OUT (Y1 + Y2 + Y3 + Y4 + Y5 + Y6 + Y7); ADDER [IN1, IN2, IN3, IN4, IN5, IN6, IN7, OUT] end var end process ------------------------------------------------------------------------------- end module