module ARCH_3B (FUNCTIONS, CHANNELS, VARIABLE, VARIABLE_ARRAY, MESI_CACHE) is ------------------------------------------------------------------------------- -- Architecture of systems communicating by means of N+1 shared variables, N -- of which are represented as the cells a[0], ..., a[N-1] of an N-variable -- array, the (N+1)th variable being represented by a separate process. ------------------------------------------------------------------------------- process Arch_3b [NCS: Pid, CS: Access, A, B: Operation, MU: Latency] is par NCS, CS, A, B in Protocol [NCS, CS, A, B] || L [NCS, CS, A, B, MU] end par end process ------------------------------------------------------------------------------- -- Auxiliary process for compositional generation: protocol without latencies ------------------------------------------------------------------------------- process Protocol [NCS: Pid, CS: Access, A, B: Operation] is par A, B in par P [NCS, CS, A, B] (0 of Pid) || P [NCS, CS, A, B] (1 of Pid) || P [NCS, CS, A, B] (2 of Pid) || P [NCS, CS, A, B] (3 of Pid) end par || par Variable_Array [A] (0 of Nat) || Variable [B] (0 of Nat) end par end par end process ------------------------------------------------------------------------------- -- Auxiliary process for inserting latencies ------------------------------------------------------------------------------- process L [NCS: Pid, CS: Access, A, B: Operation, MU: Latency] is var a: Cache_Array, a_i, b: Cache, index, pid: Pid, acc: Access, op: Operation, cop: Cached_Operation in a := cache_array (cache (Invalid)); b := cache (Invalid); loop alt A (?op, ?index, ?any Nat, ?pid); a_i := a[Nat (index)]; cop := update_caches (pid, op, !?a_i); a[Nat (index)] := a_i; MU (cop, pid) [] B (?op, ?any Nat, ?pid); cop := update_caches (pid, op, !?b); MU (cop, pid) [] CS (?acc, ?pid); if acc == Enter then MU (acc, pid) end if [] NCS (?pid); MU (Work, pid) end alt end loop end var end process end module